ERSA'07: June 27, 2007 Schedule

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6:45am - 5:00pm:  Registration (Second Floor, Conference Lobby: 1-5)


SESSION 4-ERSA:   TASK SCHEDULING AND DYNAMIC RECONFIGURATION
                  Chair: Prof. David Andrews, Univ. of Kansas, USA
                  June 27, 2007 (Wednesday); 08:20am - 11:00am
                  (LOCATION: Gold Room)

08:20 - 08:40am:  HW Implementation of a Task Manager for Reconfigurable Systems
                  Javier Resano, Juan Antonio Clemente, Carlos Gonzalez,
                  Jose Luis Garcia, and Daniel Mozos
                  Universidad Complutense de Madrid, Spain

08:40 - 09:00am:  Task Partitioning for the Scheduling on Reconfigurable
                  Systems Driven by Specification Self-Similarity
                  Matteo Giani, Massimo Redaelli, Marco D. Santambrogio,
                  and Donatella Sciuto
                  Politecnico di Milano, Italy

09:00 - 09:20am:  Configuration and Data Scheduling for Executing Dynamic
                  Applications onto Multi-Context Reconfigurable Architectures
                  F. Rivera, M. Sanchez-Elez, and N. Bagherzadeh
                  Depto. Arquitectura de Computadores y Automatica, Spain

09:20 - 09:30am:  SHORT BREAK

09:30 - 10:00am:  Distinguished Paper
                  Design of Homogeneous Communication Infrastructures for
                  Partially Reconfigurable FPGAs
                  Jens Hagemeyer, Boris Kettelhoit, Markus Koester, and Mario Porrmann
                  University of Paderborn, Germany

10:00 - 10:20am:  A Compiler to Generate Hardware from Java Byte Codes for High
                  Performance, Low Energy Embedded Systems
                  Darrin Hanna, Michael DuChene, Lawrence Kennedy, and Brian Carpenter
                  Oakland University, USA

10:20 - 10:40am:  BREAK

10:40 - 11:00am:  Selecting Heterogeneous Computation Blocks for Reconfigurable
                  JPEG Codec Computing
                  Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, and
                  Chung-Ping Chung
                  National Chiao Tung University, Taiwan

11:00 - 11:45am:  Invited Talk
                  Scientific Computing using Reconfigurable Hardware
                  Viktor Prasanna
                  University of Southern California, Los Angeles, California, USA


11:45 - 01:00pm:  LUNCH (On Your Own)

SESSION 5-ERSA:   RECONFIGURABLE HARDWARE, II
                  Chair: Prof. Paul Chow, Univ. of Toronto, Canada
                  June 27, 2007 (Wednesday); 01:00pm - 02:20pm
                  (LOCATION: Gold Room)

01:00 - 01:20pm:  Reducing Critical Path Delay in FPGAs with SRAM Tables Shared
                  by NPN-Equivalent Functions
                  Jason J. Meyer and Fatih Kocan
                  Southern Methodist University, USA

01:20 - 01:40pm:  Latency Optimization for a Reconfigurable, Self-Timed, and
                  Bit-Serial Architecture
                  Achim Rettberg, Florian Dittmann, and Raphael Weber
                  University Paderorn, Germany

01:40 - 02:00pm:  An FPGA Implementation of Reciprocal Sums for SPME
                  Sam Lee and Paul Chow
                  University of Toronto, Canada

02:00 - 02:20pm:  Pure ASIC-Based Retargetable Computing: Architectures,
                  Advantages, and Challenges
                  Yong-Kyu Jung
                  Texas A&M University, USA

02:20 - 02:40pm:  Closing remarks, T. Plaks


06:00 - 09:00pm:  FOUR TUTORIALS  (planned)

                  Factor Graphs for Advanced Algorithm Design in Wireless Communications
                  Dr. Henk Wymeersch
                  Massachusetts Institute of Technology, Cambridge, Massachusetts, USA
                  Location: Ballroom 2

                  Data Mining in Time Series and Multimedia Databases
                  Dr. Eamonn Keogh
                  University of California - Riverside, California, USA
                  Location: Ballroom 1

                  Cryptographic Features and Applications in Java (and C++)
                  Prof. Ray Kresman
                  Bowling Green State University, USA
                  Location: Ballroom 4

                  Mobile Terminal Software Architecture - Present and Future
                  S. Vijay Anand
                  General Manager, SASKEN Communication Technologies Limited - CTO Team, India
                  Location: Ballroom 3

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