ERSA'08: July 15, 2008 Schedule

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6:45am - 5:00pm:  Registration (Second Floor, Conference Lobby: 1-5)


08:00 - 10:40am:  During this period, ERSA'08 attendees are encouraged to participate
                  in sessions belonging to PDPTA'08, GCA'08, CDES'08, ESA'08, or
                  FECS'08.  These sessions discuss topics that overlap the scope
                  of ERSA'08.


SESSION 2-ERSA:   RECONFIGURABLE COMPUTING FOR SPACE BASED APPLICATIONS
                  Chair: Dr. Aravind R. Dasu, Utah State University, USA
                  July 15, 2008 (Tuesday); 10:40am - 01:20pm
                  (LOCATION: Gold Room)

10:40 - 11:20am:  Distinguished Paper:
                  TMR with More Frequent Voting for Improved FPGA Reliability
                  Brian Pratt, Michael Caffrey, Derrick Gibelyou, Paul Graham,
                  Keith Morgan, and Michael Wirthlin
                  Brigham Young University, USA; Los Alamos National Laboratory, USA

11:20 - 11:40am:  An Introduction to Radiation-Induced Failure Modes and
                  Mitigation Methods For Xilinx SRAM-Based FPGAs
                  Heather Quinn, Keith Morgan, Paul Graham, Jim Krone, Michael Caffrey,
                  and Michael Wirthlin
                  Los Alamos National Laboratory, USA; Brigham Young University, USA

11:40 - 12:00pm:  Multiparadigm Computing for Space-Based Synthetic Aperture Radar
                  Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, & Alan D. George
                  University of Florida, USA

12:00 - 12:20pm:  Scalable FPGA Architecture for DCT Computation Using Dynamic
                  Partial Reconfiguration
                  Jian Huang, Matthew Parris, Jooheung Lee, and Ronald F. DeMara
                  University of Central Florida, USA

12:20 - 01:20pm:  LUNCH (On Your Own)


01:20 - 02:00pm:  Invited Talk:
                  Reconfigurable Mesh Techniques and Applications
                  Jerry L. Trahan
                  Louisiana State University, USA
                  (LOCATION: Gold Room)


SESSION 3-ERSA:   RECONFIGURABLE SYSTEM DESIGN TOOLS AND LANGUAGES
                  Chair: Dr. Khaled Benkrid, University of Edinburgh, UK
                  July 15, 2008 (Tuesday); 02:00pm - 03:20pm
                  (LOCATION: Gold Room)

02:00 - 02:20pm:  SystemC-Based Custom Reconfigurable IP Cores for Wireless Applications
                  Ali Ahmadinia, Balal Ahmad, Ahmet Erdogan, and Tughrul Arslan
                  The University of Edinburgh, Scotland, United Kingdom

02:20 - 02:40pm:  Optimizing Pipelining in HDL Generated Automatically From C Source Codes
                  Wesley Holland and Yoginder S. Dandass
                  Mississippi State University, USA

02:40 - 03:00pm:  A Framework to Improve IP Portability on Reconfigurable Computers
                  Miaoqing Huang, Ivan Gonzalez, Sergio Lopez-Buedo, & Tarek El-Ghazawi
                  The George Washington University, USA

03:00 - 03:20pm:  High Level Languages for Reconfigurable Computing: An Equivalent
                  to Third Generation Software Languages?
                  Gavin Smith and Grant Wigley
                  University of South Australia, Australia

03:20 - 03:40pm:  BREAK


SESSION 4-ERSA:   ADAPTIVE AND DYNAMICALLY RECONFIGURABLE SYSTEMS
                  Chair: TBA
                  July 15, 2008 (Tuesday); 03:40pm - 06:00pm
                  (LOCATION: Gold Room)

03:40 - 04:00pm:  Communication and Synchronization in Multithreaded
                  Reconfigurable Computing Systems
                  Enno Luebbers and Marco Platzner
                  University of Paderborn, Germany

04:00 - 04:20pm:  A New High Performance Multi Gigabit String Matching Engine
                  Adouko G., Charot F., and Wolinski C.
                  IRISA, INRIA, University of Rennes 1, France

04:20 - 04:40pm:  System on a Programmable Chip Adaptation Through Active
                  Partial Reconfiguration
                  Erik Anderson, Matthew French, and Dong-In Kang
                  University of Southern California, USA

04:40 - 05:00pm:  A Quantitative Study of the Routing Architecture Exploring
                  Routing Locality Property for Better Performance and Routability
                  Wai-Chung Tang, Catherine Lin Zhou, and Yu-Liang Wu
                  CUHK, Hong Kong

05:00 - 05:20pm:  A New Efficient Architecture for Univariate Polynomial
                  Interpolation Over GF(2^m)
                  Edgar Ferrer and Dorothy Bollman
                  University of Puerto Rico at Mayaguez, USA

05:20 - 05:40pm:  FPGA Design Framework for Partial Run-Time Reconfiguration
                  Chris Conger, Ann Gordon-Ross, and Alan George
                  University of Florida, USA

05:40 - 06:00pm:  Elemental Computing
                  Joseph Hassoun, Steven Kelem, Brian Box, Stephen Wasson,
                  Robert Plunkett, and Chris Phillips
                  Element CXI, USA


06:30 - 07:00pm:  Industrial Workshop:
                  Architectural Synthesis for Reconfigurable Computing
                  Chris Eddington
                  Synplicity Inc.
                  (LOCATION: Gold Room)


07:15 - 08:45pm:  POSTER SESSION FOR SHORT PAPERS (Chair: TBA)
                  (LOCATION: Gold Room)

                  O. Dynamically Reconfigurable FFTs for Cognitive Radio on a
                     Multiprocessor Platform
                     Qiwei Zhang, Karel H. G. Walters, Andre B. J. Kokkeler,
                     and Gerard J. M. Smit
                     University of Twente, The Netherlands
                  O. SCARS: Scalable Self-Configurable Architecture for Reusable
                     Space Systems
                     Adarsha Sreeramareddy, Jeff G. Josiah, and Ali Akoglu
                     University of Arizona, USA
                  O. A 770ns Holographic Reconfiguration of a Four-Contexts DORGA
                     Mao Nakajima and Minoru Watanabe
                     Shizuoka University, Japan
                  O. Selection and Use of Programmable Logic in Flight Applications
                     Gary Block, Paula J. Pingree, and Yunling Lou
                     Jet Propulsion Laboratory, California Institute of Technology, USA
                  O. High Performance Double Precision Reduction Circuit
                     Implementation in FPGA
                     Andrea Suardi, Antonio Manenti, and Angelo Geraci
                     Politecnico di Milan, Italy
                  O. Hardware/Software Co-Designed Extended Kalman Filter on an FPGA
                     Robert Barnes and Aravind Dasu
                     Utah State University, USA
                  O. Multi-Criteria Optimization and Performance Measurement of
                     Domain-Specific Reconfigurable Architectures Targeting Image
                     and Video Processing Applications
                     Arjun K. Pai and Khaled Benkrid
                     Queen's University Belfast, United Kingdom;
                     The University of Edinburgh, United Kingdom


06:00 - 09:30pm:  Tutorials (please see the list of tutorials)

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