WORLDCOMP'08 Tutorial: S. C. Smith, W. K. Al-Assadi, and Jia Di
Scott C. Smith 1, Waleed K. Al-Assadi 2, and Jia Di 3
1 University of Arkansas, Department of Electrical Engineering / Associate Professor / USA
2 Missouri University of Science and Technology (formerly University of Missouri - Rolla), Department of Electrical & Computer Engineering / Assistant Professor / USA
3 University of Arkansas, Department of Computer Science and Computer Engineering / Assistant Professor / USA
Date: July 15, 2008 (6:00 - 9:30 PM)
Location: Copper Room
The development of synchronous circuits currently dominates the semiconductor design industry. However, there are major limiting factors to the synchronous, clocked approach, including the increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, increasing power consumption, timing closure effort, and difficulty with design reuse. Asynchronous (clockless) circuits require less power, generate less noise, produce less electro-magnetic interference (EMI), and allow for easier reuse of components, compared to their synchronous counterparts, without compromising performance. As the demand continues for designs with higher performance, higher complexity, and decreased feature size, asynchronous paradigms will become more widely used in the industry, as evidenced by the International Technology Roadmap for Semiconductors’ (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. ITRS predicts that asynchronous circuits will account for 19% of chip area within the next 5 years, and 30% of chip area within the next 10 years. To meet this growing industry need, chip designers should familiarize themselves with asynchronous design to make themselves more marketable and more prepared for the challenges faced by the digital design community for years to come.
This workshop will provide an introduction to asynchronous logic, by comparing competing asynchronous paradigms to each other and to the synchronous paradigm. It will then focus on delay-insensitive asynchronous circuit design using NULL Convention Logic (NCL). Specifically, combinational circuit design, pipelining optimization, and NULL Cycle Reduction will be detailed. Testability issues, automated synthesis and optimization, and power reduction techniques will also be discussed. At the end of this workshop, participants will be familiar with the advantages of asynchronous circuits, the challenges to asynchronous design being integrated into the mainstream semiconductor design industry, and will be able to design throughput-optimal NCL systems.
Participants need not have any prior knowledge of asynchronous circuit design, but should be familiar with basic logic design concepts, such as Boolean algebra and Karnaugh maps.
Biography of Instructors
Dr. Scott C. Smith is an expert in asynchronous digital design. He wrote his Ph.D. dissertation on the subject, specifically focusing on design and optimization of NULL Convention Logic circuits. After becoming an assistant professor at the University of Missouri – Rolla in 2001,
Dr. Smith has continued his research efforts in asynchronous design, resulting in 10 journal and 19 conference publications on the subject, which can be viewed at: http://comp.uark.edu/~smithsco/. He is currently working on integrating his asynchronous synthesis and optimization methods into the industry-standard CAD tools, using Tcl scripts that call C-programs, such that asynchronous circuit design will follow a very similar process and utilize the same tools as synchronous circuit design, which will expedite the integration of widespread asynchronous circuit usage in the semiconductor industry, thus alleviating many of today’s clock and power related problems.
Dr. Smith is the PI, along with Drs. Al-Assadi and Di, on an NSF CCLI Phase II project to integrate asynchronous digital design and testing into the Computer Engineering curriculum throughout the nation. The preliminary results from this project include course modules, sample problems, and NCL design libraries, all of which can be viewed and downloaded from: http://comp.uark.edu/~smithsco/CCLI_async.html.
Dr. Waleed K. Al-Assadi came to University of Missouri – Rolla (UMR) from industry. He has over 8 years of industrial experience in the major semiconductor companies. He spent two years as a Sr. Development Design Engineer with Advanced Micro Devices, Texas Microprocessors Division, and 6 years as Advisory Engineer with IBM PowerPC Embedded Processors, IBM Microelectronics. He joined UMR in August 2003, and has since been focusing his research and teaching efforts on VLSI design and testing, including design-for-test (DFT) methodologies for asynchronous circuits.
Dr. Jia Di’s expertise is in low power digital circuit design and hardware security. His Ph.D. dissertation was on energy-aware design and analysis for synchronous and asynchronous circuits. During his Ph.D. study, he developed a transistor-level power estimation method for NCL threshold gates, a probabilistic gate-level switching activity estimation method for NCL circuits, and an energy-aware NCL circuit design technique. After joining the Computer Science and Computer Engineering department at University of Arkansas as an assistant professor in 2004, Dr. Di has continued his research on power reduction for NCL circuits, while expanding his research to the hardware security area. He has developed a bit-wise completion energy-aware NCL circuit design technique to further improve power reduction and reduce overhead, and has applied NCL circuits to space-related applications to demonstrate their wide-temperature sustainability. Dr. Di has also extended NCL to a dual-spacer dual-rail delay-insensitive logic (D3L) to mitigate power and timing based side-channel attacks.